The invention concerns adjusting the output impedance of a line interface to accommodate the impedance of a transmission line with taps for the efficient coupling of power to the transmission line. More particularly, the invention concerns a line interface and a method for matching the output impedance of a transceiver with the input impedance of a transmission line with taps. More particularly, the invention concerns the efficient output of a maximum amount of power to the transmission line.
High bit rate digital service lines (HDSL) are used to transmit digitized information over standard telephone lines. In this and other telephony applications, the transmission line is commonly referred to as a xe2x80x9cloopxe2x80x9d. A common problem with full-duplex communication over a loop with taps is inefficient power output to the loop due, to an impedance mismatch at the interface between the loop and a transceiver.
One or more taps may exist at various locations on a loop. These taps, which are provided for future connection to the loop are typically unloaded. Loop impedance Zloop is a function of the location and number of taps in the loop. A tap located near an end of the loop can significantly affect the value of Zloop. Accordingly, if due to the presence taps, the value of Zloop differs from the value of Zout which characterizes an output impedance driving the loop, signal power transferred to the loop will be reduced.
The ANSI T1E1.4196-006 and ETS1 ETR 152 standards define ten test loops for a transceiver. The loops are designated as one through ten. Because of taps, the loop impedance of some of the loops, for example the loops designated two, seven, and nine, are known to be xe2x80x9cproblematicxe2x80x9d at the customer premises (CP) side of a loop. The remaining loops (one, three-six, eight, and ten) are deemed xe2x80x9cnon-problematicxe2x80x9d because they exhibit loop impedances that are relatively unaffected by taps. In this regard, Zloop for one ANSI loop configuration (say, loop 2) may be in excess of 110 ohms, while the loop impedance for one of the problematic loops may be about 20 ohms. Consequently, a transceiver designed to drive the first loop will very inefficiently drive the problematic loop. Table 2B in the appendix lists the input impedances of loop 6 and loop 2 at several frequencies fi of interest. Table 2C in the appendix lists the input impedances of loop 7 and loop 9 at several frequencies of interest. Loop 6 is an example of a loop without taps. Loops 2, 7, and 9 are examples of loops with taps close to the CP side of the loops.
FIG. 1 illustrates a circuit commonly used as an interface to a loop 25. A shortcoming of this circuit is that the output impedance Zout of the interface is matched to only one value of input impedance Zloop of the loop 25.
For the circuit shown in FIG. 1:
Zout=2RL(n2)+Rtr≈135 ohms,
where,
RL=RL1=RL2≈16.7 ohms,
n≈2, (with xe2x80x9cnxe2x80x9d being the ratio of the number of turns N2 of the secondary of the transformer T to number of turns N1 of the primary of the transformer T), and
Rtr≈1.4 ohms, (with Rtr being the winding resistance of the primary side of the transformer T).
Generally, Zloop=R+jX. In the circuit illustrated in FIG. 1, for the case when the loop has no taps, for frequencies f greater than 100 kHz, X equals about 0, R equals about 108 ohms, and consequently Zloop equals about 108 ohms. For frequencies f less than 100 kHz, X equals about xe2x88x921/jwc, R equals about 108 ohms, as a consequence Zloop may be greater than about 135 ohms. Thus, for the case of no taps connected to the loop, 135 ohms is a reasonable estimate of the value of Zloop for frequencies both greater than and less than 100 kHz. A simplified schematic diagram of the relationship between Zout and Zloop is illustrated in FIG. 2. For the circuits of FIGS. 1 and 2, Zout=Zloop≈135 ohms, and the transfer function T(s)=Zloop/(Zout+Zloop)=xc2xd. Therefore, when there are no taps on the loop, the impedance matching between Zout and Zloop is good, and consequently the output power is maximum, frequency performance distortions are minimum, and there is no phase shift. A further benefit is good echo cancellation in received signals via operation of a hybrid 30.
FIG. 3 illustrates the transformer T and the loop 25 of the circuit of FIG. 1, but with a tap 45 in the loop near the CP end of the loop. For the circuit illustrated in FIG. 3, in the frequency band of interest, which is about 80 KHz to about 400 KHz, the value of Zloop is complex and, for example, will drop to about 20xc2x1j20 ohms. Zout remains equal to about 135 ohms. Consequently, the impedances no longer match and power output to the loop is reduced. A simplified schematic diagram of the relationship between Zout and Zloop in this case is illustrated in FIG. 4. The transfer function T(s) is as follows: T(s)=20xc2x1j20/((135+(20+j20)). As a result of the poor impedance matching, the output power drops by a factor of about ten, frequency performance distortions are relatively high, there is phase shift distortion, and the echo of the transmitted signal is inadequately removed from signals received from the loop. Thus, the performance of the circuit of FIG. 1 is maximally efficient without taps in the loop, because, due to the fixed values of R1 and RL2, the circuit is optimized for only one value of Zloop. In practice, the value of Zloop may vary from one loop to another, and there is a need for an interface that automatically matches its output impedance Zout to the impedances of various loops, for example the ten loops defined by the ANSI standard.
A collateral problem with full-duplex communication over a loop is that the transmitted signal""s echo (TE) becomes mixed with the signal received from the loop. Line interfaces typically have a line coupling transformer, for coupling the signal to be transmitted into the loop. The line coupling transformer will typically have a first winding and a second winding, with the second winding being connected to the loop. A voltage referred to as Vecho is present at the first winding. Vecho consists of an aggregate of both a received signal and TE. TE may be considerably larger than the received signal. The received signal, therefore, may be significantly corrupted by TE. It is desirable to remove TE from Vecho in order to produce a signal that consists of only the received signal. TE is commonly removed from Vecho with a subtractor, which subtracts an estimate of TE from Vecho.
The circuit of FIG. 1 also subtracts an approximation of TE from Vecho, thereby reducing the amount of TE coexisting with the received signal. To accomplish this, the signal to be transmitted is tapped after the power amplifiers and is input to a hybrid 30. Ideally, the output of the hybrid is an accurate replica of TE, which is subtracted from the aggregate of the received signal and TE.
Vecho (amplified at 35) and the output of the hybrid are input into a subtractor 40, where the output of the hybrid is subtracted from the output of the amplifier 35. As a result of the subtraction, TE is removed from the amplified Vecho signal to the extent that the output of the hybrid is an accurate replica of TE. However, the output of the hybrid will be an accurate replica of TE only when the input impedance of the loop Zloop, equals the value of Zloop used for the design of the hybrid.
An objective of this invention is to provide a line interface apparatus that automatically matches the output impedance Zout of the apparatus to the loop impedance Zloop of one of several loops with taps that may be coupled to the line interface apparatus, in order to provide for efficient power transfer. Secondary objectives are the reduction of nonlinearities and cancellation of echo signals. The line interface apparatus is for coupling a signal to a loop with taps for transmission. The loop is characterized by the impedance Zloop The line interface apparatus will generally be used in conjunction with, or as part of, a telecommunications device, for example, a modem. The line interface apparatus will typically be used for the transmission and reception of signals over high bit rate digital service lines (HDSL), or the equivalent.
The line interface apparatus includes a line coupling transformer that has first and second windings. The line interface apparatus also includes a variable impedance circuit that is connected to the first winding of the line coupling transformer. The variable impedance circuit includes an impedance that may be selectively and automatically changed to maximize the efficiency with which signal power is coupled to a loop with taps. The variable impedance circuit adjusts the output impedance Zout of the line interface apparatus so that it may match, or substantially equal, the loop impedance Zloop of a loop.
The variable impedance circuit operates by switching impedances into the connection between the output of a transceiver amplifier and the first winding of the line coupling transformer. The impedances may be reactive, or entirely resistive.
The impedances are automatically switched in response to the magnitude of an echo signal detected by the line interface apparatus.
In a first embodiment, the variable impedance circuit includes at least a first reactive section and a second reactive section, wherein the first reactive section is characterized by a first impedance, and the second reactive section that is characterized by a second impedance. The variable impedance circuit further includes a switch circuit that is connected to the first and second reactive sections and to the first winding of the line coupling transformer, for switching either the first or the second reactive section in series with the first winding of the line coupling transformer. The switch circuit includes a switch and a second transformer. The second transformer inductively couples the first or the second reactive section in series with the first winding of the line coupling transformer, depending on the position of a switch arm of the switch.
The line interface apparatus may further include a filter section connected to the variable impedance circuit, in which case the apparatus is referred to as a telecommunications apparatus. The filter section may comprise a high pass filter (HPF) and a low pass filter (LPF). The filter section reduces nonlinearities and crosstalk. The apparatus may further include means for generating signals to be transmitted over the line and receiving signals from the line, in which case the apparatus is referred to as a modem. The means for generating signals can be a signal source.
In the first embodiment, the line interface apparatus automatically determines whether to switch either the first or the second reactive section in series with the first winding of the line coupling transformer. This is accomplished by using a hybrid to produce a replica of TE, and then using a subtractor to subtract the output of the hybrid from a signal generated across the first winding of the line coupling transformer, referred to as Vecho. Vecho comprises a composite of the received signal, and TE.
The output of the hybrid will be an accurate replica of Vecho only when Zloop is equal to the value of Zloop used for the design of the hybrid. A value of Zloop similar to the impedance of a group of non-problematic loops is used for the design of the hybrid. Accordingly, the output of the hybrid will be an accurate replica of TE when a non-problematic loop is connected to the second winding of the coupling transformer, and the output of the hybrid will not be an accurate replica of TE when a problematic loop is connected to the second winding of the coupling transformer.
TE has a much larger amplitude than the received signal. Thus, if the output of the hybrid is not an accurate replica of TE, the amplitude of Vs the output of the subtractor will be much greater than if the output of the hybrid is an accurate replica of the TE. This occurs because, if the output of the hybrid is an accurate replica of TE, then TE will be subtracted out in the subtractor, reducing the amplitude of Vs. Accordingly, the magnitude of the output of the subtractor Vs is an indication of whether the output of the hybrid is an accurate replica of TE, which will only occur when Zloop equals the value of Zloop used for the design of the hybrid. The amplitude of Vs therefore indicates the efficiency of power transfer from the line interface apparatus to the loop.
The output Vs of the subtractor is input into a digital signal processor (DSP), where the amplitude of Vs is compared to a threshold value. An output of the DSP is connected to a control input of the switch, to connect the arm of the switch to either the first reactive section or the second reactive section.
The first reactive section is designed to have an impedance characteristic of the problematic loops, and the second reactive section is designed to have an impedance characteristic of the non-problematic loops. The value of Zloop used for the design of the hybrid is representative of the impedances of the non-problematic loops. Thus, when the line interface apparatus is connected to any of the non-problematic loops, the output of the hybrid will be an accurate replica of TE. In this case the output of the subtractor will be less than the threshold value, and signal from the output of the DSP will cause the arm of the switch to be connected to the second reactive section, which causes Zout to be substantially equal to the impedance of any of the non-problematic loops. If the line interface apparatus is connected to any one of the problematic loops, the hybrid will not produce an accurate replica of TE. In this case the output of the subtractor will be at least as great as the threshold value, and the arm of the switch will be connected to the first reactive section, which causes Zout to be substantially equal to the impedance of any of the problematic loops. Thus, Zout is automatically matched to Zloop when the line interface apparatus is connected to either a non-problematic or a problematic loop. This impedance matching results in more efficient power transfer to the loop, reduces nonlinearities, and enhances echo signal cancellation.
In a second embodiment of the invention, the variable impedance circuit includes at least two resistors, one of which is switched into the signal path between the power amplifier and the first winding in response to the DSP output. This embodiment achieves the desired maximization of efficiently, but tolerates inefficient. hybrid operation, with a consequent reduction in the effectiveness of echo cancellation.